1. Field of the Invention
The present invention relates to a liquid crystal display device. More particularly, the present invention relates to a liquid crystal display device having a device driver with low power consumption and low heat generation. The present invention also includes a method for driving the liquid crystal display device with the device driver.
2. Description of the Related Art
A liquid crystal display device controls light transmittance through individual liquid crystal cells. The transmittance through each individual liquid crystal cell is controlled in accordance with a corresponding video signal. The video signals control the light transmittance through the liquid crystal cells to display a picture.
There are several liquid crystal display types. One such display type known as an active matrix liquid crystal display device allows rapid switching of the transmittance states through each individual crystal cell. Accordingly, active-matrix devices are frequently used to display pictures that rapidly change over time, such as motion pictures. Rapid switching of the liquid crystal cells in an active matrix display device is achieved using a thin film transistor (hereinafter, referred to as “TFT”) as a switching device.
A schematic block diagram of one example of a liquid crystal display device and corresponding driver of the related art is shown in FIG. 1. The liquid crystal display device includes a liquid crystal display panel 2 where a plurality of data lines 5 and a plurality of gate lines 6 cross each other. A plurality of TFT's are respectively formed for driving liquid crystal cells in the areas where each data line crosses a corresponding gate line. A data driver 3 is used to provide data to the data lines 5, and a gate driver 4 is used to provide a scan pulse to the gate lines 6. A timing controller 1 is used to generate the various signals that are used to control and/or operate the data driver 3 and the gate driver 4.
The liquid crystal display panel 2 has a liquid crystal injected between an upper and lower glass substrate. The data lines 5 and the gate lines 6 are formed perpendicular to one another on the lower glass substrate. A TFT is formed where each data line 5 and gate line 6 cross one another. At this junction, the gate electrode of the TFT is connected to a corresponding gate line 6 and the source electrode of the TFT is connected to a corresponding data line 5. The drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell. Further, a storage capacitor is formed on the lower glass substrate of the liquid crystal display panel 2 for sustaining the voltage of the liquid crystal cell at various voltage levels to which it has been charged.
The timing controller 1 employs a number of different signals to carry out its various functions. For example, it receives digital video data RGB from, for example, an external source, and provides it to the data driver 3. Other signals that may be provided to the timing controller 1 or generated by it include a horizontal synchronization signal H, a vertical synchronization signal V and a clock signal CLK. In the illustrated example, the timing controller 1 generates a gate driver control signal GDC for provision to the gate driver 4 and a data driver control signal DDC for provision to the data driver 3. The data driver control signal DDC may be comprised of a number of different signals such as, for example, a source shift clock SSC, a source start pulse SSP, a polarity control signal POL, a source output enable signal SOE. The gate control signal GDC may be comprised of a number of different signals such as, for example, of a gate start pulse GSP, a gate shift clock GSC, a gate output enable signal GOE.
As noted above, the gate driver 4 may be in the form of a shift register that sequentially generates the scan pulse. For example, the gate driver sequentially generates the scan pulse in response to the state of the gate control signal GDC received from the timing controller 1. The gate driver 4 may also include a level shifter for shifting the voltage of the scan pulse to a level which is suitable for driving the liquid crystal cell. Finally, the gate driver 4 may also include an output buffer. The gate driver 4 supplies the scan pulse sequentially to each gate line 6, thereby turning on the corresponding TFT's connected to the respective gate line 6. This results in the selection of one horizontal row of liquid crystal cells to which a pixel drive voltage corresponding to the RGB data, i.e., an analog gamma compensation voltage, is supplied. The pixel voltages for the individual liquid crystal cells of the row of the active gate line 6 are provided by the data driver 3 to the respective liquid crystal cells.
The data driver 3 supplies the data to the data lines 5 in response to the data drive control signal DDC supplied from the timing controller 1. The data driver 3 samples the digital data RGB from the timing controller 1, latches the data, and then converts the data to, for example, an analog gamma voltage for use in as the pixel drive voltage. The data driver 3 may be implemented as one or more monolithic integrated circuits (hereinafter, referred to as “IC”) 3A having the configuration shown in FIG. 2. To this end, all of the components of the IC 3A may be implemented on a single monolithic integrated circuit or as separate integrated circuits.
Each of the data ICs 3A, as shown in FIG. 2, include a data register 21 that receives the digital video data RGB from the timing controller 1. Each of the data ICs 3A also comprises a shift register 22 for generating a sampling clock; a first latch 23, a second latch 24, a digital/analog converter (hereinafter, referred to as “DAC”) 25 and an output circuit 26. Output circuit 26 includes a plurality of data lines DL1 to DLk. Further components used in or by the IC 3A include a gamma voltage supplier 27 connected between a gamma reference voltage generator (not shown) and the DAC 25. The gamma reference voltage generator provides stable upper and lower gamma voltage references, GH and GL, respectively, to the gamma voltage supplier 27.
The data register 21 supplies the digital video data RGB from the timing controller 1 to the first latch 23. The shift register 22 shifts the source start pulse SSP from the timing controller 1 in accordance with the source sampling clock SSC to generate a sampling signal. Further, the shift register 22 shifts the source start pulse SSP to transmit a carry signal CAR to the shift register 22 of the next stage. The first latch 23 sequentially samples the digital data RGB from the data register 21 in response to the sampling signal received from the shift register 22. The second latch 24 latches the data received from the first latch 23, and then concurrently outputs the latched data in response to the state of the source output enable signal SOE received from the timing controller 1. The DAC 25 converts the digital video data that it receives from the second latch 24 into gamma voltages based on the voltages DGH, DGL that it receives from the gamma voltage suppler 27. The gamma voltages provided at the outputs of the DAC 25 are analog voltages corresponding to the gray levels of the digital video data RGB. The output circuit 26 receives the gamma voltages from the DAC 25 and provides them to the input of the output circuit 26. The output circuit 26, in turn, is connected to provide an analog driving signal to each of the data lines 5. The gamma voltage supplier 27 subdivides the range of gamma reference voltages, GH and GL provided from the gamma reference voltage generator to supply the gamma voltages corresponding to each gray level to the DAC 25.
As the size and visual requirements of such liquid crystal displays have increased, the load, frequency of operation, and the amount of heat generated by data IC 3A have likewise increased. The generation of excess heat by the data IC 3A, has been a factor in decreasing the driving reliability of the data IC 3A. A major cause of heat generation in the data IC 3A is the amount of current that must flow through the output buffers of the output circuit 26. An exemplary output buffer is shown at 26A of FIG. 3. As illustrated, the data IC 3A consumes power as it acts as a current Isource, and a current sink, Isink. The Isource and Isink currents flow through resistive components of the output buffer 26A resulting in the generation of excess heat.
Recently, several methods for driving the liquid crystal cells of a liquid crystal display have been developed to improve the charging characteristics of the liquid crystal cell. One such method is known as the charge share method. In accordance with the charge share method, a given data line is driven to a single shared voltage level VShare in the time between successive outputs of the actual data voltage levels on the given data line. One example of the output signals provided to a data line using the charge share method is shown in FIG. 4. As can be seen in this figure, a substantial amount of current flows through the output buffer 26A in an output buffer driving section as the voltage on the data line transitions from the shared voltage VShare to the data voltage. As a result of this flow of current during these transitions, heat generation and the power consumption are substantial.
Another method for driving the liquid crystal cells of a liquid crystal display is known as the pre-charge method. In accordance with this method, a given data line is alternately driven to one of two voltage levels, +Vpre or −Vpre, between successive outputs of the actual pixel drive signals on the same data line. One example of the output signals provided to a data line using the pre-charge method is shown in FIG. 5. As can be seen in this figure, the voltage transitions experienced by the output buffer 26A have been somewhat reduced through the use of the pre-charge voltages +Vpre, −Vpre. But, the temperature of the data IC 3A is increased and the power consumption is rapidly increased in the pre-charge driving area 51, 52 of the low data voltage due to the pre-charge voltage +Vpre, −Vpre supplied from the outside, where it is high, in the data voltage which is a mean or less. Therefore, further performance improvement of the pre-charge method is needed.